Novel area-time efficient static CMOS totally self-checking comparator
Document Type
Article
Date of Original Version
2-1-1993
Abstract
The comparator is an essential element in concurrent error detection (CED). To ensure the correctness of error detection processes, comparators must be totally self-checking (TSC): any single fault occurring in the comparator must be detected by at least one normal input pattern, and before the detection of that fault, no erroneous output must be guaranteed. In this paper, an area-time efficient static CMOS TSC comparator design is presented. This comparator uses only eight transistors and is totally self-checking with respect to stuck-at faults, stuck-open, stuck-on, briding faults, and breaks.
Publication Title, e.g., Journal
IEEE Journal of Solid-State Circuits
Volume
28
Issue
2
Citation/Publisher Attribution
Lo, Jien Chung. "Novel area-time efficient static CMOS totally self-checking comparator." IEEE Journal of Solid-State Circuits 28, 2 (1993): 164-168. https://digitalcommons.uri.edu/ele_facpubs/829