Fault-tolerant content addressable memory
Document Type
Conference Proceeding
Date of Original Version
12-1-1993
Abstract
In this paper, we analyze the error behavior of content addressable memories and provide necessary and sufficient conditions to protect them. Single error tolerant designs are demonstrated for bit- and byte-organized content addressable memories. This level of protection is equivalent to that of the conventional ECC protection in memory subsystems.
Publication Title, e.g., Journal
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Citation/Publisher Attribution
Lo, Jien Chung. "Fault-tolerant content addressable memory." Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (1993): 193-196. https://digitalcommons.uri.edu/ele_facpubs/828
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