Fault-tolerant content addressable memory

Document Type

Conference Proceeding

Date of Original Version



In this paper, we analyze the error behavior of content addressable memories and provide necessary and sufficient conditions to protect them. Single error tolerant designs are demonstrated for bit- and byte-organized content addressable memories. This level of protection is equivalent to that of the conventional ECC protection in memory subsystems.

Publication Title, e.g., Journal

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

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