Concurrent error detection IC in 2-μm static CMOS logic
Document Type
Article
Date of Original Version
5-1-1994
Abstract
When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code disjoint (SCD) built-in current sensor (BICS). This chip was fabricated by MOSIS using 2 μm p-well CMOS technology. In chip tests, all implanted faults, including analog faults, were detected as expected. We also show that the self-exercising mechanism of the SCD BICS is indeed functioning properly. This is the first demonstration of working static CMOS CED chip.
Publication Title, e.g., Journal
IEEE Journal of Solid-State Circuits
Volume
29
Issue
5
Citation/Publisher Attribution
Lo, Jien-Chung, Shih Yao Sun, and James C. Daly. "Concurrent error detection IC in 2-μm static CMOS logic." IEEE Journal of Solid-State Circuits 29, 5 (1994): 580-584. doi: 10.1109/4.284710.