Date of Award
2025
Degree Type
Thesis
Degree Name
Master of Science in Computer Engineering
Department
Electrical, Computer, and Biomedical Engineering
First Advisor
Resit Sendag
Abstract
This work proposes replacing fully static ASIC functional units with programmable functional units that leverage tightly integrated programmable logic within CPU cores. The programmable units can be configured to match the execution behavior of a specific workload while still allowing the CPU to remain general-purpose across all workloads. This approach reduces the total area required for functional units without sacrificing performance. We evaluate two configurations: an Ideal implementation, where programmable and ASIC functional units have equal area, and an Area-Larger implementation, where programmable units occupy twice the area of their ASIC counterparts. To establish feasibility, we first conduct binary instrumentation and micro-op analysis of the x86 instructions executed across several benchmarks. The results indicate strong potential for this approach, as each benchmark exercised only a subset of available functional units. Simulations of a CPU core equipped with programmable functional units show that performance remains unchained with up to a 60% functional-unit area reduction in the Ideal configuration and up to 50% area reduction in the Area-Larger configuration. Furthermore, repurposing the saved area to increase L1D or L1I cache capacity yields an average performance improvement of 5.8%.
Recommended Citation
Pollard, Jonathan, "EXPLORING AREA AND PERFORMANCE BENEFITS OF PROGRAMMABLE LOGIC INTEGRATED CPU CORE" (2025). Open Access Master's Theses. Paper 2683.
https://digitalcommons.uri.edu/theses/2683