Date of Award


Degree Type


Degree Name

Doctor of Philosophy in Electrical Engineering


Electrical and Computer Engineering

First Advisor

Jien-Chung Lo


This dissertation addresses both the consequences and advantages of the fact that all digital logic implementations are analog in reality. Although, in the ideal sense, all digital signals exist at either a logic 0 or a logic 1, in practice signals are generally between these two extreme values. There is a poorly-defined zone (which we denote as φ) near the midpoint of the logic range where a logic level is not recognizable as a 0 or 1 beyond a reasonable doubt. Variations in design and fabrication exacerbate this uncertainty. We introduce the concept of zoned binary, which has three states { 0, φ, 1 }, and arbitrarily define ¢ as consisting of the logic voltage range between 1/3Vdd and 2/3Vdd, although the designer is free to set the boundary at any other levels appropriate to the specific implementation. It is pointed out that there are many physical causes why a logic value might be in the φ zone, including insufficient time to settle to a static value, wire and device defects, and noise. It is noted that current techniques focus on avoidance, or detection of and dealing with effects. We introduce the idea of an unknown value as information, and suggest that it can be used to enhance performance. We design and test a detector for φ, and proceed to apply it to rudimentary practical problems such as interconnect difficulties, and to more demanding applications such as asynchronous systems and communications error correction. A new logic family - Binary Plus logic - is proposed, designed and validated, in both static and dynamic versions. Its applicability to completion-detection requirements of asynchronous circuitry is shown, and an asynchronous stage is designed, fabricated and tested. The detection of φ in a received communications bit is interpreted as an error location method. It is shown that this information can be used with techniques well documented in the literature to enhance the error correction capability of existing error-control coding schemes. A 9-bit simple parity-based circuit capable of correcting received bits in the state is designed, fabricated and shown to perform properly.



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