Date of Original Version
A thermomechanical model to describe the mechanisms of polishing pad scratching in chemical–mechanical planarization (CMP) has been formulated and investigated. CMP is a necessary process in integrated circuit (IC) fabrication to planarize wafers with nanoscale features after patterned layer deposition. Polishing pad asperities can produce microscale scratches on the wafer surface during CMP, reducing IC manufacturing yields. The constructed thermomechanical model accounts for stresses of the pad and wafer contact and also provides the means to track input energy dissipation during CMP. Tracking energy dissipation offers information about processes that may influence scratch production. This knowledge ultimately produces a greater physical understanding of CMP for the prevention of pad scratching. Polishing pad stress relaxation experiments demonstrate the importance of viscoelastic and plastic strain energy dissipation with its effects on the wafer stress field. Scratch producing ability of the polishing pad is found to decrease with use in CMP, with slurry soaking and increasing polishing time. Mechanical behavior of the polishing pad is demonstrated to differ when in compression and in tension. Compressibility of the pad material is shown to be significant in stress modeling through experimental measurement of polishing pad volume change. Differential scanning calorimetry of used polishing pad samples revealed energy dissipation into the polishing pad surface with increasing polishing time of CMP. Energy dissipation processes influence pad scratching in CMP. Analytical wafer stress field modeling unveils that the scratching ability of a polishing pad decreases when it is less stiff or has a smoother surface.
Ponte, D.C. & Meyer, D.M.L. J Mater Sci: Mater Electron (2016) 27: 1745. doi: 10.1007/s10854-015-3949-4