Improving data cache performance via address correlation: An upper bound study
Date of Original Version
Address correlation is a technique that links the addresses that reference the same data values. Using a detailed source-code level analysis, a recent study  revealed that different addresses containing the same data can often be correlated at run-time to eliminate on-chip data cache misses. In this paper, we study the upper-bound performance of an Address Correlation System (ACS), and discuss specific optimizations for a realistic hardware implementation. An ACS'can effectively eliminate most of the LI data cache misses by supplying the data from a correlated address already found in the cache to thereby improve the performance of the processor. For 10 of the SPEC CPU2000 benchmarks, 57 to 99% of all LI data cache load misses can be eliminated, which produces an increase of 0 to 243% in the overall performance of a superscalar processor. We also show that an ACS with 1-2 correlations for a value can usually provide comparable performance results to that of the upper bound. Furthermore, a considerable number of correlations can be found within the same set in the LI data cache, which suggests that a low-cost ACS implementation is possible. © Springer-Verlag 2004.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Chuang, Peng Fei, Resit Sendag, and David J. Lilja. "Improving data cache performance via address correlation: An upper bound study." Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 3149, (2004): 541-550. doi:10.1007/978-3-540-27866-5_71.