Multiple-valued caches for power-efficient embedded systems
Document Type
Conference Proceeding
Date of Original Version
9-20-2005
Abstract
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded systems. Multiple-valued caches have significant potential for compact and power-efficient cache array design. The cache models differ from each other depending on whether they store tag and data in binary, radix-r or a mix of both. Our analytical study of cache silicon area shows that an embedded System-on-a-chip (SoC) equipped with a multiple-valued cache model can reduce the cache data storage area up to 6% regardless of cache parameters. Also, our experiments on several embedded benchmarks demonstrate that dynamic cache energy consumption can be reduced up to 62% in a multiple-valued instruction cache in an embedded SoC. © 2005 IEEE.
Publication Title, e.g., Journal
Proceedings of The International Symposium on Multiple-Valued Logic
Citation/Publisher Attribution
Özer, Emre, Resit Sendag, and David Gregg. "Multiple-valued caches for power-efficient embedded systems." Proceedings of The International Symposium on Multiple-Valued Logic (2005): 126-131. https://digitalcommons.uri.edu/ele_facpubs/956