Single fault masking logic designs with error correcting codes
Document Type
Conference Proceeding
Date of Original Version
12-1-1995
Abstract
Triple modular redundancy (TMR) has been the most popular method in reliable logic designs due to its single fault masking capability. However, the reliability of a TMR design can be improved only by enhancing the reliabilities of the components. This paper examines the use of error correcting codes in reliable logic design. The goal is to provide an equivalent single fault masking capability as that of TMR scheme. Further, by reducing the level of hardware redundancy, a higher reliability can be achieved. Design examples are given to illustrate the key issues in single fault masking logic designs with error correcting codes. Reliabilities of different single fault masking carry lookahead adder designs are also examined.
Publication Title, e.g., Journal
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Citation/Publisher Attribution
Lo, Jien Chung. "Single fault masking logic designs with error correcting codes." IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1995): 296-304. https://digitalcommons.uri.edu/ele_facpubs/823