Reliable logic circuits with byte error control codes - a feasibility study
Document Type
Conference Proceeding
Date of Original Version
12-1-1996
Abstract
This paper addresses the relations between logic circuit synthesis, error model and error control codes so that the efficient reliable logic circuits can be obtained. We propose that single fault masking capability of a random logic circuit can be obtained by encoding its outputs in a byte error correcting code; this is equivalent to that of the triple modulo redundancy (TMR) technique. Similarly, byte error detecting code can be used to provide an equivalence of duplication. In this paper, we address the problems and issues related to the realization of byte-organized configuration where the byte error control codes can be applied. Some MCNC benchmark circuits are used as examples to demonstrate the feasibility of the proposed concept.
Publication Title, e.g., Journal
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Citation/Publisher Attribution
Lo, Jien Chung, Masato Kitakami, and Eiji Fujiwara. "Reliable logic circuits with byte error control codes - a feasibility study." IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1996): 286-294. https://digitalcommons.uri.edu/ele_facpubs/818