Efficient parity prediction in FPGA
Document Type
Article
Date of Original Version
1-1-2001
Abstract
We propose, in this paper, XOR-based decomposition methods to implement parity prediction circuits efficiently in field programmable gate arrays (FPGAs). The first proposed method is an extension of the Shannon's expansion theorem. Such extension enables us to force decomposing the parity prediction circuit into appropriate size sub-circuits. The second proposed method is based on the Reed-Muller canonical form that transforms AND/OR Boolean functions to AND/XOR functions. The XOR relation enables us to find more efficient grouping for the parity prediction function. The MCNC benchmark circuits are used to demonstrate the effectiveness of the proposed techniques. © 2001 IEEE.
Publication Title, e.g., Journal
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Citation/Publisher Attribution
Ko, Seok Bum, Tian Xia, and Jein Chung Lo. "Efficient parity prediction in FPGA." IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (2001): 176-181. doi: 10.1109/DFTVS.2001.966767.