Analysis of a BICS-only concurrent error detection method
Document Type
Article
Date of Original Version
3-1-2002
Abstract
We propose in this paper a BICS-only method for concurrent error detection (CED) where a built-in current sensor (BICS) will be solely responsible for detecting faults and errors. Due to the wide applicability of the BICS, this approach can be applied directly to combinational circuits, sequential circuits, and even some analog circuits. A dependability model was developed to study the effectiveness of the proposed BICS-only method. The unsafe probability of the BICS-only design is sensitive to both fault coverage and testability of the BICS. When used in a duplicated CED system for fault masking, the system reliability is sensitive to the fault coverage, but not to the testability of the BICS. Next, we show that a dramatic increase in unsafe probability is possible if the BICS cannot make detection at every system clock cycle. A higher testability for BICS will, contrary to our intuition, make the unsafe probability higher. For duplicated CED applications, the reliability will be even lower than that of a nonredundant system. Therefore, the design criteria for BICS in the BICS-only method, in the order of importance, are: operating speed, fault coverage, and testability.
Publication Title, e.g., Journal
IEEE Transactions on Computers
Volume
51
Issue
3
Citation/Publisher Attribution
Lo, Jien Chung. "Analysis of a BICS-only concurrent error detection method." IEEE Transactions on Computers 51, 3 (2002): 241-253. doi: 10.1109/12.990124.