Title
A novel technology mapping method for AND/XOR expressions
Document Type
Conference Proceeding
Date of Original Version
7-21-2003
Abstract
In this paper, we propose a novel technology mapping technique for Look-Up Table (LUT) - based Field Programmable Gate Arrays (FPGA). The proposed technology mapping technique is based on AND/exclusive-OR (XOR) expressions. The AND/XOR nature of the proposed techniques can map many important XOR-intensive applications, such as error detecting/correcting, data encryption/decryption, and computer arithmetic circuits efficiently in FPGA. The typical EDA tools deal mainly with AND/OR expressions and therefore are quite inefficient for XOR-intensive applications. We design a new approach and conduct experiments using MCNC benchmark circuits in FPGA environment to demonstrate the effectiveness of our proposed technology mapping technique. The proposed technique is superior to the typical methods with respect to area. When using the proposed technique, the number of CLB is reduced by 67.6 % (speed-optimized one) and 57.7 % (area-optimised one) and the total number of equivalent gate counts is also reduced by 65.5 % compared to the typical methods.
Publication Title, e.g., Journal
Proceedings of The International Symposium on Multiple-Valued Logic
Citation/Publisher Attribution
Ko, Seok Bum, and Jien Chung Lo. "A novel technology mapping method for AND/XOR expressions." Proceedings of The International Symposium on Multiple-Valued Logic (2003): 133-138. https://digitalcommons.uri.edu/ele_facpubs/800