Efficient realization of parity prediction functions in FPGAs
Date of Original Version
In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods.
Journal of Electronic Testing: Theory and Applications (JETTA)
Ko, Seok Bum, and Jien Chung Lo. "Efficient realization of parity prediction functions in FPGAs." Journal of Electronic Testing: Theory and Applications (JETTA) 20, 5 SPEC.ISS. (2004): 489-499. doi:10.1023/B:JETT.0000042513.15382.e7.