A new hierarchy cache scheme using RAM and pagefile
Document Type
Article
Date of Original Version
1-1-2004
Abstract
One newly designed hierarchical cache scheme is presented in this article. It is a two-level cache architecture using a RAM of a few megabytes and a large pagefile. Majority of cached data is in the pagefile that is nonvolatile and has better IO performance than that of normal data disks because of different data sizes and different access methods used. The RAM cache collects small writes first and then transfers them to the pagefile sequentially in large sizes. When the system is idle, data will be destaged from the pagefile to data disks. We have implemented the hierarchical cache as a filter driver that can be loaded onto the current Windows 2000/Windows XP operating system transparently. Benchmark test results show that the cache system can improve IO performance dramatically for small writes. © Springer-Verlag 2004.
Publication Title, e.g., Journal
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume
3189
Citation/Publisher Attribution
Liu, Rui Fang, Change Sheng Xie, Zhi Hu Tan, and Qing Yang. "A new hierarchy cache scheme using RAM and pagefile." Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 3189, (2004): 515-526. doi: 10.1007/978-3-540-30102-8_43.