Delay chain based programmable jitt+er generator

Document Type

Conference Proceeding

Date of Original Version



In this paper, we presents a programmable jitter generator. Different from the traditional jitter generator that uses the analog phase modulation (PM) technique to generate only non-Gaussian distributed jitter components, the proposed jitter generator uses digital techniques. It consists of a voltage controlled delay chain, jitter control block, and some basic digital components. It can generate not only the non-Gaussian distributed jitter component, but also the Gaussian-distributed jitter component. In addition, almost all jitter characteristics are controllable. This jitter generator can be used in jitter tolerance test and jitter transfer function measurement. A Xilinx XC4010 FPGA chip is used to validate this design. © 2004 IEEE.

Publication Title, e.g., Journal

Proceedings - Ninth IEEE European Test Symposium, ETS 2004

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