Delay chain based programmable jitt+er generator
Date of Original Version
In this paper, we presents a programmable jitter generator. Different from the traditional jitter generator that uses the analog phase modulation (PM) technique to generate only non-Gaussian distributed jitter components, the proposed jitter generator uses digital techniques. It consists of a voltage controlled delay chain, jitter control block, and some basic digital components. It can generate not only the non-Gaussian distributed jitter component, but also the Gaussian-distributed jitter component. In addition, almost all jitter characteristics are controllable. This jitter generator can be used in jitter tolerance test and jitter transfer function measurement. A Xilinx XC4010 FPGA chip is used to validate this design. © 2004 IEEE.
Proceedings - Ninth IEEE European Test Symposium, ETS 2004
Xia, Tian, Peilin Song, Keith A. Jenkins, and Jien Chung Lo. "Delay chain based programmable jitt+er generator." Proceedings - Ninth IEEE European Test Symposium, ETS 2004 , (2004): 16-21. https://digitalcommons.uri.edu/ele_facpubs/797