BUGS - A bottom-up cache structure for networked storage servers
Document Type
Conference Proceeding
Date of Original Version
12-17-2004
Abstract
This paper introduces a new caching structure to improve server performance by minimizing data traffic over the system bus. The idea is to form a bottom-up caching hierarchy in a networked storage server. The bottom level cache is located on an embedded controller that is a combination of a network interface card (NIC) and a storage host bus adapter (HBA). Storage data coming from or going to a network are cached at this bottom level cache and meta-data related to these data are passed to the host for processing. When cached data exceed the capacity of the bottom level cache, some data are moved to the host RAM that is usually larger than the bottom level cache. This new cache hierarchy is referred to as bottom-up cache structure (BUCS) in contrast to a traditional CPU-centric top-down cache where the top-level cache is the smallest and fastest, and the lower in the hierarchy the larger and slower the cache. Such data caching at the controller level dramatically reduces bus traffic and leads to great performance improvement for networked storages. We have implemented a proof-of-concept-prototype using Intel's IQ80310 reference board and Linux network block device. Through performance measurements on the prototype implementation, we observed up to 3 times performance improvement of BUCS over traditional systems in terms of response time and system throughput.
Publication Title, e.g., Journal
Proceedings of the International Conference on Parallel Processing
Citation/Publisher Attribution
Zhang, Ming, and Qing Yang. "BUGS - A bottom-up cache structure for networked storage servers." Proceedings of the International Conference on Parallel Processing (2004): 310-317. doi: 10.1109/ICPP.2004.1327937.