Title
Design of a compact direct digital frequency synthesizer with 12 bit amplitude and 32 bit frequency resolution
Document Type
Conference Proceeding
Date of Original Version
12-1-1996
Abstract
This paper describes the design of a monolithic direct digital frequency synthesizer. The circuit realizes a 12 bit output sine wave with a frequency resolution of 32 bit. The core of the 1.2 μm CMOS implementation consists of approximately 6,000 transistors and occupies an area not larger than 1.5 mm2. The circuit is aimed at a maximum tuning range of 100 MHz, or equivalently, a clock rate of 200 MHz. This upper value yields a minimum frequency increment of 0.023 Hz. The system exhibits a total latency of 14 clock periods.
Publication Title, e.g., Journal
IEEE Workshop on VLSI Signal Processing, Proceedings
Citation/Publisher Attribution
Fischer, G., and N. K. Modadugu. "Design of a compact direct digital frequency synthesizer with 12 bit amplitude and 32 bit frequency resolution." IEEE Workshop on VLSI Signal Processing, Proceedings (1996): 75-82. https://digitalcommons.uri.edu/ele_facpubs/235