Digital correction of circuit imperfections in cascaded Σ-Δ modulators composed of 1^ST-order sections

Authors

Alan J. Davis, University of Rhode Island
Godi Fischer, University of Rhode IslandFollow
Hans Helge Albrecht, University of Rhode Island
Juergen Hess, University of Rhode Island

Document Type

Conference Proceeding

Date of Original Version

1-1-2000

Abstract

An approach to remove the effects of amplifier finite gain and C-ratio mismatches in the 1-1-1 (MASH) and the 1-1-1-1 cascaded sigma-delta modulator is presented. By correcting the digital outputs with estimates of the parasitic errors due to analog circuit imperfections, uncancelled quantization noise terms can be removed. A 1-1-1-1 cascaded modulator, implemented as a fully differential switched-capacitor circuit, has been fabricated in a 1.2 μm, double-poly, n-well CMOS process. Measurements of the modulator verify that for an amplifier gain of 60 dB, C-Ratio mismatch errors of 0.52% and 0.054%, the error correction offers an overall improvement in SNDR of 12-22 dB. A 12 μVrms sine wave can be restored with a positive SNDR.

Publication Title, e.g., Journal

Proceedings - IEEE International Symposium on Circuits and Systems

Volume

5

Citation/Publisher Attribution

Davis, Alan J., Godi Fischer, Hans H. Albrecht, and Juergen Hess. "Digital correction of circuit imperfections in cascaded Σ-Δ modulators composed of 1^ST-order sections." Proceedings - IEEE International Symposium on Circuits and Systems 5, (2000). https://digitalcommons.uri.edu/ele_facpubs/229