Title

Novel content addressable memory

Document Type

Article

Date of Original Version

1-1-1989

Abstract

The design and performance of a content addressable memory (CAM) LSI using a newly developed cell circuit is presented. The LSI has all the functions necessary to implement a high-speed data searching system and is fabricated using a 3μm CMOS double-metallisation process. A cycle time of 60 ns with the basic associative operation taking 20 ns has been measured. © 1989, The Institution of Electrical Engineers. All rights reserved.

Publication Title

Electronics Letters

Volume

25

Issue

8

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