Novel content addressable memory
Document Type
Article
Date of Original Version
1-1-1989
Abstract
The design and performance of a content addressable memory (CAM) LSI using a newly developed cell circuit is presented. The LSI has all the functions necessary to implement a high-speed data searching system and is fabricated using a 3μm CMOS double-metallisation process. A cycle time of 60 ns with the basic associative operation taking 20 ns has been measured. © 1989, The Institution of Electrical Engineers. All rights reserved.
Publication Title, e.g., Journal
Electronics Letters
Volume
25
Issue
8
Citation/Publisher Attribution
Ghosh, D., J. C. Daly, and J. Fried. "Novel content addressable memory." Electronics Letters 25, 8 (1989): 524-526. doi: 10.1049/el:19890359.
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