On-chip current sensing circuit for CMOS VLSI
Document Type
Conference Proceeding
Date of Original Version
1-1-1992
Abstract
CMOS is a popular technology today for very large scale integrated (VLSI) circuits. But, conventional functional testing cannot guarantee the detection of some defects. Built-in current testing has been suggested to enhance the defect coverage. In this paper, the authors present a high-speed built-in current sensing (BICS) circuit design. An experimental CMOS VLSI chip containing BICS is described. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short circuit defects and some open circuit defects at a clock speed of 30 MHz (limited by the test set up). SPICE3 simulations indicate a defect detection time of 2 ns.
Publication Title, e.g., Journal
Proceedings of the IEEE VLSI Test Symposium
Volume
1992-April
Citation/Publisher Attribution
Shen, Tung Li, J. C. Daly, and Jien-Chung Lo. "On-chip current sensing circuit for CMOS VLSI." Proceedings of the IEEE VLSI Test Symposium 1992-April, (1992): 309-314. doi: 10.1109/VTEST.1992.232771.
