A fast binary adder with conditional carry generation
Document Type
Article
Date of Original Version
12-1-1997
Abstract
This brief contribution presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 μm static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit. © 1997 IEEE.
Publication Title, e.g., Journal
IEEE Transactions on Computers
Volume
46
Issue
2
Citation/Publisher Attribution
Lo, Jien Chung. "A fast binary adder with conditional carry generation." IEEE Transactions on Computers 46, 2 (1997). doi: 10.1109/12.565614.
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