Erasure error correction with hardware detection
Document Type
Conference Proceeding
Date of Original Version
12-1-1999
Abstract
Error-control coding methods have been the primary method used to protect digital communications from transmission errors. Such codes are well understood, and their capabilities for error detection and correction clearly established in the literature. For correction purposes, error location is required; for this reason error-control codes' detection capabilities significantly exceed their correction capabilities. If error location information can be determined and supplied prior to processing by code-checking circuitry, such correction capability can be significantly enhanced in special circumstances. One such circumstance is that of bit `erasures'. This work focuses on the use of undefined logic levels (near neither Vdd nor Vss) as an erasure detection method. It is shown how the error correction capabilities of error-correction codes of various dmin are enhanced by pre-detection of erasures. An implementation example is presented: this 9-bit parity-based erasure correction circuit is described; test results of the fabricated circuit are presented as a comparison with capabilities of a simple parity checker. Specific details of extension to higher-order codes are presented.
Publication Title, e.g., Journal
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Citation/Publisher Attribution
Armitage, William D., and Jien Chung Lo. "Erasure error correction with hardware detection." IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1999). https://digitalcommons.uri.edu/ele_facpubs/1832