An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits

Document Type

Article

Date of Original Version

4-2024

Department

Electrical, Computer and Biomedical Engineering

Abstract

This paper introduces an FPGA-enabled framework to accelerate the automated design process for Photonic Integrated Circuit (PIC) devices. PICs are foreseen as a foundation for the next-generation semiconductors. However, the complexity of PIC design presents considerable challenges. Machine Learning (ML) techniques have shown promise in the realm of PIC design. The primary hurdle, however, is the extended training duration, solely constrained by the slow electromagnetic (EM) Finite-Difference Time-Domain (FDTD) solver. We propose a fast framework with a dedicated FPGA FDTD accelerator tailor-designed to speed up the PIC simulation. Benchmarking was carried out against commercial tools, with the single-FPGA accelerator outperforming both a multicore CPU and a GPU cluster. We taped out and evaluated the PIC devices designed through the proposed framework, and the experimental outcomes aligned. This demonstrates the full design circle, showcasing that the proposed framework enabled by FPGA breaks the current bottleneck in this domain.

This study was conducted entirely on a commercial cloud platform (AWS), leveraging CPUs, FPGAs, and GPUs, with FPGA programming efficiently executed using High-Level Synthesis (HLS) and the Xilinx Runtime (XRT). The FPGA, along with its modern development tools, is seamlessly integrated into a heterogeneous computing platform, showcasing the accessible and practical nature of this approach. Our findings show the exciting possibility that ML-based physical design could be notably sped up enabled by FPGAs in a cloud-hosted heterogeneous cluster as a service.

Publication Title, e.g., Journal

FPGA '24: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

Publisher Statement

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