Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor

Authors

Qing Yang, University of Rhode Island
Laxmi N. Bhuyan, University of Louisiana at Lafayette
Bao Chyn Liu, University of Louisiana at Lafayette

Document Type

Article

Date of Original Version

1-1-1989

Abstract

The use of private caches in a multiprocessor system causes inconsistency of the shared data among the caches and among caches and the main memory. A large number of protocols have been proposed to solve this coherence problem. In this paper, we develop analytical models for seven existing cache protocols, namely: Write-Once, Write-Through, Synapse, Berkeley, Illinois, Firefly, and Dragon. The protocols are implemented on a multiprocessor with a packet-switched shared bus. The models are based on queueing networks that consist of both open and closed classes of customers. The models incorporate the requests for invalidation signals, write-through, and write-back operations and the solution is based on the mean value analysis (MVA) algorithm. Performance comparison among these protocols under various system parameters is carried out based on our models. © 1989 IEEE

Publication Title, e.g., Journal

IEEE Transactions on Computers

Volume

38

Issue

8

Citation/Publisher Attribution

Yang, Qing, Laxmi N. Bhuyan, and Bao Chyn Liu. "Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor." IEEE Transactions on Computers 38, 8 (1989): 1143-1153. doi: 10.1109/12.30868.