A novel cache design for vector processing
Document Type
Conference Proceeding
Date of Original Version
1-1-1992
Abstract
An innovative cache design for vector computers, called a prime-mapped cache, is introduced. By utilizing the special properties of a Mersenne prime, the design does not increase the critical path length of a processor or the cache access time as compared to a direct-mapped cache. The prime-mapped cache minimizes cache miss ratio caused by line interferences. It is shown that significant performance gains are possible by adding the proposed cache memory into an existing vector computer provided that application programs can be blocked. The performance gain will increase with the increase of the speed gap between processors and memories. An analytical performance model based on a generic vector computation model is developed to study the performance of the design. A preliminary performance analysis on various vector access patterns shows that the prime-mapped cache can provide as much as a factor of 2 to 3 performance improvement over the conventional direct-mapped cache in the vector processing environment, and the additional hardware cost is negligible.
Publication Title, e.g., Journal
Conference Proceedings - Annual Symposium on Computer Architecture
Citation/Publisher Attribution
Yang, Qing, and Liping Wu Yang. "A novel cache design for vector processing." Conference Proceedings - Annual Symposium on Computer Architecture (1992): 362-371. doi: 10.1145/146628.140398.