A one's complement cache memory
Document Type
Conference Proceeding
Date of Original Version
1-1-1994
Abstract
Most of today's microprocessors have an on-chip cache to reduce average memory access latency. These on-chip caches generally have low associativity and small sizes. Cache line conflicts are the main source of cache misses which are essential to overall system performance. This paper introduces an innovative, conflict-free cache design, called one's complement cache. By means of parallel computation of cache addresses and memory addresses of data, the new design does not increase critical hit time of cache accesses. Cache misses caused by line interferences are minimized by means of evenly distributing data items referenced by program loops across all sets in a cache. Evenly distribution of data in the cache is achieved by making the number of sets in the cache a prime or an odd number thereby the chance of related data being mapped to a same set is small. Trace-driven simulations are used to evaluate the performance of the new design. Performance results on a set of programs from SPEC92 benchmarks show that the new design improves cache performance over the conventional set-associative cache by about 100% with negligibly additional hardware cost. © 1994 IEEE.
Publication Title, e.g., Journal
Proceedings of the International Conference on Parallel Processing
Volume
1
Citation/Publisher Attribution
Yang, Qing, and Sridhar Adina. "A one's complement cache memory." Proceedings of the International Conference on Parallel Processing 1, (1994). doi: 10.1109/ICPP.1994.39.