A comparative analysis of cache designs for vector processing
Document Type
Article
Date of Original Version
12-1-1999
Abstract
This paper presents an experimental study on cache memory designs for vector computers. We use an execution-driven simulator to evaluate vector cache performance of a set of application programs from Perfect Club and SPEC92 benchmark suites. Our simulation results uncover a few important facts which were unknown before: First of all, the prime-mapped cache that we newly proposed shows great performance potential in vector processing environment. Because of its conflict-free property, the prime-mapped cache performs significantly better than conventional cache designs for all applications considered. Second, performance results on the benchmarks indicate that data locality in vector processing does exist, although the effects of line size, associativity, replacement algorithm, and prefetching scheme on cache performance are very different from what has been commonly believed. A medium size vector cache (e.g., 128Kbytes) eliminates the necessity for a large number of interleaved memory banks in vector computers. Our experiments show that the vector computer that has a medium size prime-mapped cache with small cache line size and limited amount of prefetching provides significant speedup over conventional vector computers without cache. Performance results reported in this paper can also provide guidance to general-purpose computer designers to enhance cache performance for numerical applications. © 1998 IEEE.
Publication Title, e.g., Journal
IEEE Transactions on Computers
Volume
48
Issue
3
Citation/Publisher Attribution
Sun, Tong, and Qing Yang. "A comparative analysis of cache designs for vector processing." IEEE Transactions on Computers 48, 3 (1999): 331-344. doi: 10.1109/12.754999.