Going beyond worst-case specs with TEAtime
Document Type
Article
Date of Original Version
3-1-2004
Abstract
The timing-error-avoidance method continuously modulates a computer-system clock's operating frequency to avoid timing errors even when presented with worst-case scenarios. The timing-error-avoidance prototype provides a circuit and system solution to such problems for synchronous digital systems. TEAtime has demonstrated much better performance than classically designed systems and also adapts well to varying temperature and supply-voltage conditions.
Publication Title, e.g., Journal
Computer
Volume
37
Issue
3
Citation/Publisher Attribution
Uht, Augustus K.. "Going beyond worst-case specs with TEAtime." Computer 37, 3 (2004): 51-56. doi: 10.1109/MC.2004.1274004.
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