Title

Ultra-Low Power PLL Design and Jitter Anaylsis

Date of Award

2013

Degree Type

Dissertation

Abstract

This thesis presents the design of ultra-low power Phase-Locked Loops (PLLs) intended for applications in the extended audio range. The PLL is well suited for battery operated systems, where small size and low power operation are crucially important. The two implementations presented are based on current controlled relaxation oscillator and a ring oscillator intended for the same frequency range. The frequency is controlled by a current that can vary from 2 to 74 nA. Using a reference frequency of ¼ of the typical watch crystal frequency, the user can select any integer multiple of 8.192 kHz up to the maximum of 122.88 kHz. The PLL circuits operate from a single 3 V supply and, depending on the actual output frequency, dissipate between 0.9-2 micron watt of power.

This work also investigates phase jitter in PLLs. Expressions for the period jitter caused by the current noise as well as the voltage noise present on the two rails (Vdd and Vref) are derived. The theoretical results reveal that the current noise establishes a lower bound for jitter, which scales as the inverse of the square root of the selected current. The numerical result has been put to test by two practical circuits, which consume between 300-660 nA of current and produce frequencies between 8.192-122.88 kHz. The measurements confirmed that the computed lower bound serves as a realistic estimate of the actual performance.

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