Date of Award


Degree Type


Degree Name

Master of Science in Electrical Engineering (MSEE)


Electrical Engineering

First Advisor

Qing Yang


This thesis evaluates an innovative cache design called, prime-mapped cache. The performance analysis on various applications and programs shows that the prime-mapped cache performs better than the conventional cache organizations. The performance gain will increase with the increase of the speed gap between processors and memories. The exact cache behavior of numerical applications namely: matrix multiplication and SPEC benchmarks is studied by varying the cache parameters such as cachesize, linesize and associativity. Traces are collected from these programs and miss ratios for instructions and data accesses are compared. Based on the experimental results and depending on the algorithm used, the miss ratios of the prime-mapped cache are found to be 50 to 100% less than for conventional caches. Depending upon the speed difference between processors and memories, with the prime-mapped cache these algorithms can run 30% to 2 times faster than they do on conventional caches.



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