Parallelized implementation of a Genetic Algorithm on a Field Programmable Gate Array (FPGA) to provide heuristic solutions for the Capacitated Vehicle Routing Problem (CVRP)
Date of Award
Master of Science in Electrical Engineering (MSEE)
Electrical, Computer, and Biomedical Engineering
This thesis reports on the implementation of a Genetic Algorithm for finding heuristic solutions to the Capacitated Vehicle Routing Problem (CVRP) on High-Performance Field Programmable Gate Arrays (FPGAs). The heuristic approach to the class of NP-hard problems related to the Travelling-Salesman-Problem (TSP) has a long tradition in computer science, with this thesis being directly based on an implementation of a specialized Genetic Algorithm for a Graphic Processing Unit (GPU). In my work, I describe how the algorithmic structure can be directly transformed into an adapted computing architecture with special focus on the highest possible degree of parallelism. For that, the proposed design makes use of the flexibility of FPGAs and self-defined hardware in terms of data representation, parallelized computation and manipulation as well as memory management. The resulting architecture is tested in behavioral simulation for verification purposes, and bit-streamed to an actual high-performance FPGA to re-ensemble a potential Application Specific Integrated Circuit (ASIC) for logistic planning. In this configuration, state-of-the-art benchmark problems are run on the device to compare the hardware implementation with the already existing approaches on GPU and CPU (Central Processing Unit) in terms of speed, quality of solutions and energy efficiency.
Heer, Maximilian Jakob, "Parallelized implementation of a Genetic Algorithm on a Field Programmable Gate Array (FPGA) to provide heuristic solutions for the Capacitated Vehicle Routing Problem (CVRP)" (2022). Open Access Master's Theses. Paper 2240.
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