On-chip jitter measurement for phase locked loops
Date of Original Version
In this paper, we propose an efficient on-chip method for the direct measurement of jitter in phase locked loops (PLLs). The jitter is first detected as the phase difference in the form of pulses with duration in the range of pico-seconds. A combination of a modified charge pump and a binary counter can then record the number that represents the jitter measurement. This is the first attempt to directly measure the jitter of PLLs on-chip via analog testing circuit, but with digital output. The proposed testing circuit is only about 20% of the PLL under test. The proposed on-chip jitter measurement circuit is a central part of built-in self-test for many embedded applications in SOCs.
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Xia, Tian, and Jien Chung Lo. "On-chip jitter measurement for phase locked loops." Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2002-January, (2002): 399-407. doi:10.1109/DFTVS.2002.1173537.