On-chip jitter measurement for phase locked loops

Document Type

Conference Proceeding

Date of Original Version



In this paper, we propose an efficient on-chip method for the direct measurement of jitter in phase locked loops (PLLs). The jitter is first detected as the phase difference in the form of pulses with duration in the range of pico-seconds. A combination of a modified charge pump and a binary counter can then record the number that represents the jitter measurement. This is the first attempt to directly measure the jitter of PLLs on-chip via analog testing circuit, but with digital output. The proposed testing circuit is only about 20% of the PLL under test. The proposed on-chip jitter measurement circuit is a central part of built-in self-test for many embedded applications in SOCs.

Publication Title, e.g., Journal

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems