Limit cycles and pattern noise in single-stage single-bit delta-sigma modulators

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Pattern noise in single-bit delta-sigma modulators remains a phenomenon, which is not yet fully understood. To gain more insight into this problem, we have utilized state-space matrices to describe single-stage delta-sigma modulators operated under the condition of a constant input signal. We then established a procedure for characterizing and validating potential limit cycles. This enabled us to carry out an exhaustive search for cyclic sequences up to a length of 40 clock periods. Longer limit cycles have been found by means of an empirical, computationally more efficient random search method. This search algorithm has been applied to ideal and nonideal systems. By revealing power and frequency distribution of the tonal patterns, the numerical results yield a realistic estimate of the spurious free dynamic range. We also found that the majority of the potential limit cycles in an analog implementation can be eliminated by naturally occurring thermal noise. To be effective, the equivalent noise power of this natural dither signal must be on the order of the in-band quantization noise power of the modulator.

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IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications