Title

Levo - A scalable processor with high IPC

Document Type

Conference Proceeding

Date of Original Version

8-1-2003

Abstract

The Levo high IPC microarchitecture is described and evaluated. Levo employs instruction time-tags and Active Stations to ensure correct operation in a rampantly speculative and out-of-order resource flow execution model. The Tomasulo-algorithm-like broadcast buses are segmented; their lengths are constant, that is, do not increase with machine size. This helps to make Levo scalable. Known high-ILP techniques such as Disjoint Eager Execution and Minimal Control Dependencies are implemented in novel ways. Examples of basic Levo operation are given. A chip floorplan of Levo is presented, demonstrating feasibility and little cycle-time impact. Levo is simulated, characterizing its basic geometry and its performance.

Publication Title

Journal of Instruction-Level Parallelism

Volume

5

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