Levo - A scalable processor with high IPC
Date of Original Version
The Levo high IPC microarchitecture is described and evaluated. Levo employs instruction time-tags and Active Stations to ensure correct operation in a rampantly speculative and out-of-order resource flow execution model. The Tomasulo-algorithm-like broadcast buses are segmented; their lengths are constant, that is, do not increase with machine size. This helps to make Levo scalable. Known high-ILP techniques such as Disjoint Eager Execution and Minimal Control Dependencies are implemented in novel ways. Examples of basic Levo operation are given. A chip floorplan of Levo is presented, demonstrating feasibility and little cycle-time impact. Levo is simulated, characterizing its basic geometry and its performance.
Journal of Instruction-Level Parallelism
Uht, Augustus K., David Morano, Alireza Khalafi, and David R. Kaeli. "Levo - A scalable processor with high IPC." Journal of Instruction-Level Parallelism 5, (2003). https://digitalcommons.uri.edu/ele_facpubs/1124