Date of Award


Degree Type


Degree Name

Master of Science in Electrical Engineering (MSEE)


Electrical, Computer, and Biomedical Engineering

First Advisor

Resit Sendag


In modern computer systems, memory access latencies can have a significant impact on performance, and caching and prefetching are used to reduce these latencies. Caches store recently accessed data to allow the central processing unit (CPU) to access it quickly, while prefetchers attempt to predict future data requests and load them into the cache in advance.

However, the simultaneous use of different prefetchers at different levels of the cache hierarchy can be challenging, as interactions between them can potentially lead to performance degradation. As prefetchers are often designed in isolation, without considering how they interact with prefetchers at other levels, these prefetcher interactions have not been studied extensively.

Therefore, this thesis investigates these inter-level prefetcher interactions. Various prefetcher and system evaluation metrics are presented and applied using adaptations made to the simulator used. Two different approaches are introduced for the further analysis of harmful prefetcher interactions. By applying these approaches for demonstration purposes, it was possible to identify, reduce or even eliminate some performance degrading interactions between prefetchers.



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