A 2-ns Detecting Time, 2-μ m CMOS Built-in Current Sensing Circuit
Date of Original Version
Built-in current testing is known to enhance the defect coverage in CMOS VLSI. In this paper, an experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μ m p-well CMOS technology. The power bus current of an 8 x 8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some implanted open-circuit defects at a clock speed of 30 MHz (limited by the test setup). SPICE3 simulations indicate a defect detection time of about 2 ns. © 1993 IEEE
Publication Title, e.g., Journal
IEEE Journal of Solid-State Circuits
Shen, Tung Li, and Jien Chung Lo. "A 2-ns Detecting Time, 2-μ m CMOS Built-in Current Sensing Circuit." IEEE Journal of Solid-State Circuits 28, 1 (1993): 72-77. doi: 10.1109/4.179205.