Fault-tolerant associative approach to on-line memory repair
Document Type
Conference Proceeding
Date of Original Version
12-1-1994
Abstract
A fault-tolerant associative approach is proposed to be used in on-line repair for highly available memories. The memory repair mechanism is designed similar to a cache memory in its spare to main memory mapping schemes. Four spare memory mapping schemes are presented: fully associative, associative direct, associative set and associative multiple. If cache memory repair is needed, the proposed schemes can also be applied. The repair mechanism consists of a TMR content addressable memory (CAM) and an SEC/DED spare data memory. Although it is sufficient to encode the CAM with SEC code, we find that TMR version is faster in accessing time and more cost-effective. To repair a 1M×32 main memory with eight spare words, the proposed schemes use less than 0.015% of hardware redundancy
Publication Title, e.g., Journal
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Citation/Publisher Attribution
Lo, Jien Chung. "Fault-tolerant associative approach to on-line memory repair." IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1994): 168-176. https://digitalcommons.uri.edu/ele_facpubs/824