Testing the realistic bridging faults in CMOS circuits
Date of Original Version
This paper describes use of a previously proposed test generation program named Jethro to detect the bridging faults based on the pre-determined testing conditions of cells in the standard cell library. In a one-time effort, fabrication level defects (shorts) in each cell in the standard cell library are analyzed via circuit simulations by monitoring the power supply current. Test sets of each cell are then determined and pre-stored for later use. For a given circuit under test (CUT), the automatic test generation program generates the test vectors by trying to satisfy all test sets of all cells in given netlist. The dynamic compaction of the test sets is performed.
Digest of Papers - 1996 IEEE International Workshop on IDDQ Testing, IDDQ 1996
Song, Peilin, and Jien Chung Lo. "Testing the realistic bridging faults in CMOS circuits." Digest of Papers - 1996 IEEE International Workshop on IDDQ Testing, IDDQ 1996 , (1996): 84-88. doi:10.1109/IDDQ.1996.557838.