Fast and area-time efficient Berger code checkers
Date of Original Version
In this paper we extend the direct implementation of threshold functions using ratioed FET circuits presented earlier. Such designs are fast, area-time efficient and highly testable with respect to a large class of realistic defects, e.g., resistive breaks and bridges. These threshold functions were then used as core of the new Berger code checkers. For 32-bit checkers, the proposed design has a 59% speed and a 72% area-time improvements over the conventional design assuming 1.2 μm VLSI implementations.
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Guo, Yu Yau, Jien Chung Lo, and Cecilia Metra. "Fast and area-time efficient Berger code checkers." IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems , (1997): 110-118. https://digitalcommons.uri.edu/ele_facpubs/815