Title

An indirect current sensing technique for IDDQ and IDDT tests

Document Type

Conference Proceeding

Date of Original Version

1-1-2006

Abstract

An indirect current sensing technique for IDDQ and I DDT tests is proposed in this paper. This is accomplished by utilizing the pervasive on-chip voltage regulators and thus have little or no impact on CUT's design and its performance. We demonstrate that the proposed technique can be applied to both IDDQ and IDDT tests. Experiments were successfully conducted in SPICE simulations assuming the TSMC 0.18μm CMOS technology. Copyright 2006 ACM.

Publication Title

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volume

2006

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