Sigma-delta modulator architecture for wide bandwidth applications

Document Type

Conference Proceeding

Date of Original Version



This paper presents a novel approach for the robust implementation of wide-band sigma-delta modulators. The proposed architecture consists of a cascade of a third-order modulator followed by a second or third-order loop. To avoid linearity problems associated with the DAC's in the feedback paths of the modulators, both stages utilize simple ternary quantizers. To maximize the dynamic range, additional finite noise transfer function zeros have been added to the third-order stage(s). While this significantly enhances the dynamic range of the system, it does hardly affect the circuit's sensitivity with regard to some of the most prominent non-idealities such as finite amplifier open-loop gains or capacitor ratio mismatches.

Publication Title, e.g., Journal

Proceedings - IEEE International Symposium on Circuits and Systems



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