Two-stage sixth-order sigma-delta ADC with 16-bit resolution designed for an oversampling ratio of 16
Date of Original Version
This paper presents a sixth-order sigma-delta modulator capable of 16 bit resolution with an oversampling ratio (OSR) of only 16. The circuit's sensitivity to non-idealities such as amplifier finite open-loop gain, bandwidth, slew rate and capacitor mismatches is minimized through the use of a novel topology. Efficient noise shaping is realized by cascading two nearly identical third-order modulators. The dynamic range is maximized by placing a finite zero in the noise shaping function of each modulator loop. The resolution is further enhanced through the use of ternary quantizers which halve the quantization noise while avoiding the linearity problems associated with higher resolution DACs required in the modulator feedback paths. The presented modulator has been fabricated as a fully-differential switched-capacitor circuit by a 1.2μm double-poly CMOS process and operates from a ±2.5 volt power supply.
Publication Title, e.g., Journal
Midwest Symposium on Circuits and Systems
Davis, Alan J., and Godi Fischer. "Two-stage sixth-order sigma-delta ADC with 16-bit resolution designed for an oversampling ratio of 16." Midwest Symposium on Circuits and Systems 1, (1996): 230-233. https://digitalcommons.uri.edu/ele_facpubs/236