Process dependency of mosfet depletion mode MOS capacitors in series compensation
Date of Original Version
This paper discusses the realization of linear capacitors using two series connected MOS transistors in depletion mode. The efficiency of this approach is compared to poly-metal or poly-poly capacitors for several sub-micron processes. The linearity achievable with this technique is predicted for various sub-micron processes based on BSIM3 models in HSPICE. The simulations revealed a significant variation in capacitance (2% - 10%) over the usable voltage range. Incremental improvements in linearity are observed as the device geometries are scaled down. If the operation of a circuit depends on capacitor ratios only, the non-linearities of the individual capacitors can partially cancel out. Thus, despite relatively large changes in capacitance, the circuits can still achieve a high linearity. This point is illustrated by example of 2 frequently employed switched-capacitor circuits, a non-inverting integrator and a second-order bandpass/lowpass filter section.
Publication Title, e.g., Journal
Midwest Symposium on Circuits and Systems
Yung, Wai, Tian Xia, Godi Fischer, and Alan J. Davis. "Process dependency of mosfet depletion mode MOS capacitors in series compensation." Midwest Symposium on Circuits and Systems 1, (2002): I263-I266. doi: 10.1109/MWSCAS.2002.1187207.