Title

Ultra low-power phase-locked loops

Document Type

Conference Proceeding

Date of Original Version

12-1-2005

Abstract

This paper presents the design of an ultra low power Phase-Locked Loop (PLL) targeted for a frequency range of 16 kHz - 120 kHz. The PLL forms a critical component of a low power, tunable, narrow-band sonar receiver system intended to track small aquatic animals. The system is a versatile data logger capable of sensing and storing a variety of biologically interesting data such as geographic position, ambient temperature, pressure, salinity, etc. To reduce power dissipation, the PLL has been designed using CMOS logic, and all active analog components are operated in the sub-threshold region. The PLL circuit has been prototyped on a 0.5 μm CMOS test chip. The PLL is powered by a 3V supply voltage and dissipates around 5 μW of power. © 2005 IEEE.

Publication Title

Midwest Symposium on Circuits and Systems

Volume

2005

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