Introducing a New Cache Design into Vector Computers
Document Type
Article
Date of Original Version
1-1-1993
Abstract
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By utilizing the special properties of a Mersenne prime, the new design does not increase the critical path length of a processor, nor does it increase the cache access time as compared to existing cache organizations. The prime-mapped cache minimizes cache miss ratio caused by line interferences that have been shown to be critical for numerical applications by previous investigators. With negligibly additional hardware cost, we observe significant performance gains by adding the proposed cache memory into an existing vector computer. We study the performance of the new design analytically based on a generic vector computation model. The analytical model is validated through extensive simulation experiments. Our performance analysis on various vector access patterns shows that the prime-mapped cache performs significantly better than conventional cache organizations in the vector processing environment. The performance gain will increase with the increase of the speed gap between processors and memories. © 1993 IEEE
Publication Title, e.g., Journal
IEEE Transactions on Computers
Volume
42
Issue
12
Citation/Publisher Attribution
Yang, Qing. "Introducing a New Cache Design into Vector Computers." IEEE Transactions on Computers 42, 12 (1993): 1411-1424. doi: 10.1109/12.260632.