Title
A novel cache design for vector processing
Document Type
Conference Proceeding
Date of Original Version
12-1-1993
Abstract
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By utilizing the special properties of a Mersenne prime, the new design does not increase the critical path length of a processor, nor does it increases the cache access time as compared to a direct-mapped cache. The prime-mapped cache minimizes cache miss ratio caused by line interferences that have been shown to be critical for numerical applications by previous investigators. We show that significant performance gains are possible by adding the proposed cache memory into an existing vector computer provided that application programs can be blocked. The performance gain will increase with the increase of the speed gap between processors and memories. We develop an analytical performance model based on a generic vector computation model to study the performance of the design. Our preliminary performance analysis on various vector access patterns shows that the prime-mapped cache can provide as much as a factor of 2 to 3 performance improvement over the conventional direct-mapped cache in the vector processing environment. Moreover, the additional hardware cost introduced by the new mapping scheme is negligible.
Publication Title, e.g., Journal
Proceedings of the Ninth Annual International Symposium on Computer Architecture
Citation/Publisher Attribution
Yang, Qing, and Liping Wu Yang. "A novel cache design for vector processing." Proceedings of the Ninth Annual International Symposium on Computer Architecture (1993): 362-371. doi: 10.1145/146628.140398.