CAT - caching address tags. A technique for reducing area cost of on-chip caches
Date of Original Version
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique is Caching Address Tags, or CAT cache for short. The CAT cache exploits locality property that exists among addresses of memory references for the purpose of minimizing chip area-cost of address tags. By keeping only a limited number of distinct tags of cached data rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache with only a few tag entries performs as well as ordinary caches while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.
Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA
Wang, Hong, Tong Sun, and Qing Yang. "CAT - caching address tags. A technique for reducing area cost of on-chip caches." Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA , (1995): 381-390. doi:10.1109/ISCA.1995.524577.